Testing for determining the functional speed of a semiconductor device is becoming more and more challenging. Testers are typically very expensive and have difficulty applying test patterns at the high speeds that the devices under test (DUT) require, especially at the wafer.
Generally, a very significant price premium can often be placed on a device that can operate at the highest performance levels. Hence, the concept of performance sorting is employed. To enable the most revenue from a single device, a sort strategy is employed wherein a product is classified into multiple performance categories. The highest revenue is obtained when all of the devices are properly categorized. To do this, the sort approach requires precision. A device that is capable of the highest performance, but is however down-binned due to inaccurate test sorting, results in lower revenue and profit. A product that is inadvertently up-binned due to inaccurate test sorting results in customer rejection of the part and field return related expenses that can wipe out all revenue gains and customer confidence.
Designers and test engineers have implemented a number of approaches to help mitigate these issues. One such approach is to use an on-device wafer monitor or performance sort ring oscillator (PSRO) that is used to identify the relative performance of a part. This approach requires that a PSRO frequency be determined and then correlated back to the real operational frequency of the device. PSROs have limited global device wiring; they do not track the performance effects of the back end of the line (BEOL) structures, which are becoming more pronounced with smaller lithographies. PSROs are also typically composed of a single type of circuit, and as such, they do not reflect the types of circuits that make up the performance critical paths. This approach requires that significant performance guard-banding be applied, that is, providing a significant amount of tolerance for each performance level of a device, thereby reducing effective revenue.
Another approach is to use the on-device scan chains, which daisy chain all the latches together within a device as a monitor of the real performance of the device. The daisy chains include some level of global device wiring, but this method too lacks the true representative circuits and routing that define the performance critical path, as it does not have any component of combinatorial or custom logic comprising the design. This approach also requires significant amount of guard-banding.
Another example of a means to detect the performance limited paths is to attempt to duplicate the path on device and design logic to allow this path to be exercised by applying a simple pattern(s) to exercise it. This is far more effective than the above-identified testing system, but it requires a predetermination of what will ultimately be the critical path, as well as its physical realization. This also requires additional logic to be added to duplicate the critical path. This path may contain large macros and memory elements that could make reproducing this path complex and require a substantial amount of logic systems for hardware circuits. For example, U.S. Pat. No. 6,185,712, issued on Feb. 6, 2001, entitled Device Performance Optimization with Self Programmed Built-in Self Test, describes in its abstract:                An integrated circuit (IC) device wherein a built-in self test determines the IC s optimum electrical performance. A corresponding optimum performance setting is stored in NVRAM on the device. Upon each device power-up, the optimum performance setting is retrieved and provided to device control which sets the device for its best performance.        
This patent automatically generates a test sequence by utilizing a state machine to write and read an assortment of zeros and ones patterned like a checkerboard. This approach can work effectively for memories, wherein an algorithm can be specified to automatically generate the test stimulus, but it may not provide a specific and accurate indication of performance measurement for logic and microprocessors. This patent uses sense amplifiers to determine the performance of this memory specific device.
In another example,
U.S. Pat. No. 5,583,875 issued on Dec. 10, 1996, entitled Automatic Parametric Self-Testing and Grading of a Hardware System describes in its Abstract:                Automatic parametric testing of a system can be achieved by varying a parameter such as speed, voltage, and/or temperature, and then monitoring system performance. Such testing can be used to determine whether a given system meets specifications and performance variations from system to system.        
The concept of using a PLL, integrated or otherwise, with an automatic increment/decrement feature to assess performance is the main teaching of this patent. This patent also teaches a test process or procedure for employing the adjustable PLL for speed assessment and states that the result can be stored within the state of some non-volatile device. However, there is no teaching in this patent as to how performance characteristics are obtained and what performance characteristics are important.
What is needed, therefore, is an integrated self test system that will allow for testing over a wide range of devices and performance characteristics. The present invention addresses such a need.